In a continuous drive to achieve low form-factor packages, chip-to-substrate interconnect devices have evolved from conventional solder-based techniques. As microelectronic systems follow the trend toward higher functionality with ever-decreasing dimensions, the miniaturization of electrical systems has called for a much wider perspective, requiring passive components and active devices to be integrated on a single platform at both micro- and nano-scales. The “system on package” (SOP) techniques achieved earlier goals because they enabled electrical systems to be scaled, promised a paradigm shift in the way systems were perceived, and set a roadmap for ultra-miniaturization with novel interconnect solutions.
For example, one such interconnect solution involves chip-to-substrate interconnect assemblies that utilize “flip-chip” technology. In general, solder bumps were placed on an active surface of a chip, and the chip was subsequently flipped such that the solder bumps could be connected to a substrate pad. However, physical constraints due to the geometry of the interconnection became an obstacle in reducing the bump pitch or density and achieving high reliability. In addition, electro-migration issues and intermetallic formations posed additional concerns. Several interconnect assemblies have been explored to achieve ultra-fine pitch, for example, pad-to-pad gold bonding and bump-to-pad nickel bonding. Pad-to-pad gold bonding cures the aforementioned defects of solder bumps; however, the bonding is relatively expensive to make. Further, low bonding temperature cannot be achieved with bump-to-pad nickel bonding. Therefore, there is a need in the art for a fine pitch, chip-to-substrate interconnect assembly that is compatible with flip-chip technology, less costly than gold interconnects, and has the ability to handle increased input/output (I/O) density.